TR0114 VHDL Language Reference, vhdl
[ Pobierz całość w formacie PDF ]VHDL Language Reference
Summary
This comprehensive reference provides a detailed overview
of the VHDL language and describes each of the standard
VHDL keywords (reserved words).
Technical Reference
TR0114 (v1.2) September 20, 2005
VHDL is a programming language that has been designed and optimized for describing the behavior of
digital systems.
VHDL has many features appropriate for describing the behavior of electronic components ranging
from simple logic gates to complete microprocessors and custom chips. Features of VHDL allow
electrical aspects of circuit behavior (such as rise and fall times of signals, delays through gates, and
functional operation) to be precisely described. The resulting VHDL simulation models can then be
used as building blocks in larger circuits (using schematics, block diagrams or system-level VHDL
descriptions) for the purpose of simulation.
VHDL is also a general-purpose programming language: just as high-level programming languages
allow complex design concepts to be expressed as computer programs, VHDL allows the behavior of
complex electronic circuits to be captured into a design system for automatic circuit synthesis or for
system simulation. Like Pascal, C and C++, VHDL includes features useful for structured design
techniques, and offers a rich set of control and data representation features. Unlike these other
programming languages, VHDL provides features allowing concurrent events to be described. This is
important because the hardware described using VHDL is inherently concurrent in its operation.
One of the most important applications of VHDL is to capture the performance specification for a
circuit, in the form of what is commonly referred to as a test bench. Test benches are VHDL
descriptions of circuit stimuli and corresponding expected outputs that verify the behavior of a circuit
over time. Test benches should be an integral part of any VHDL project and should be created in
tandem with other descriptions of the circuit.
A standard language
One of the most compelling reasons for you to become experienced with and knowledgeable in VHDL
is its adoption as a standard in the electronic design community. Using a standard language such as
VHDL virtually guarantees that you will not have to throw away and recapture design concepts simply
because the design entry method you have chosen is not supported in a newer generation of design
tools. Using a standard language also means that you are more likely to be able to take advantage of
the most up-to-date design tools and that you will have access to a knowledge base of thousands of
other engineers, many of whom are solving problems similar to your own.
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VHDL Language Reference
Entities and Architectures
Every VHDL design description consists of at least one entity/architecture pair. (In VHDL jargon, this
combination of an entity and its corresponding architecture is sometimes referred to as a
design
entity
.) In a large design, you will typically write many entity/architecture pairs and connect them
together to form a complete circuit.
An
entity declaration
describes the circuit as it appears from the “outside” - from the perspective of its
input and output interfaces. If you are familiar with schematics, you might think of the entity declaration
as being analogous to a block symbol on a schematic.
The second part of a minimal VHDL design description is the architecture declaration. Before
simulation or synthesis can proceed, every referenced entity in a VHDL design description must be
bound with a corresponding architecture. The architecture describes the actual function – or contents –
of the entity to which it is bound. Using the schematic as a metaphor, you can think of the architecture
as being roughly analogous to a lower-level schematic referenced by the higher-level functional block
symbol.
Entity declaration
An entity declaration provides the complete interface for a circuit. Using the information provided in an
entity declaration (the names, data types and direction of each port), you have all the information you
need to connect that portion of a circuit into other, higher-level circuits, or to develop input stimuli (in
the form of a test bench) for verification purposes. The actual operation of the circuit, however, is not
included in the entity declaration.
Let's take a closer look at the entity declaration for this simple design description:
entity
compare
is
port
( A, B:
in
bit_vector(0
to
7);
EQ:
out
bit);
end
compare;
The entity declaration includes a name,
compare
, and a
port
statement defining all the inputs and
outputs of the entity. The port list includes definitions of three ports:
A
,
B
, and
EQ
. Each of these three
ports is given a direction (either
in
,
out
or
inout
), and a type (in this case either
bit_vector(0 to
7)
, which specifies an 8-bit array, or
bit
, which represents a single-bit value).
There are many different data types available in VHDL. To simplify things in this introductory circuit,
we're going to stick with the simplest data types in VHDL, which are
bit
and
bit_vector
.
Architecture declaration and body
The second part of a minimal VHDL source file is the architecture declaration. Every entity declaration
you reference in your design must be accompanied by at least one corresponding architecture (we'll
discuss why you might have more than one architecture in a moment).
Here's the architecture declaration for the comparator circuit:
architecture
compare1
of
compare
is
begin
EQ <= '1'
when
(A = B)
else
'0';
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VHDL Language Reference
end
compare1;
The architecture declaration begins with a unique name,
compare1
, followed by the name of the entity
to which the architecture is bound, in this case
compare
. Within the architecture declaration (between
the
begin
and
end
keywords) is found the actual functional description of the comparator. There are
many ways to describe combinational logic functions in VHDL; the method used in this simple design
description is a type of concurrent statement known as a
conditional assignment
. This assignment
specifies that the value of the output (
EQ
) will be assigned a value of
'1'
when
A
and
B
are equal, and
a value of
'0'
when they differ.
This single concurrent assignment demonstrates the simplest form of a VHDL architecture. As you will
see, there are many different types of concurrent statements available in VHDL, allowing you to
describe very complex architectures. Hierarchy and subprogram features of the language allow you to
include lower-level components, subroutines and functions in your architectures, and a powerful
statement known as a
process
allows you to describe complex registered sequential logic as well.
Data Types
Like a high-level software programming language, VHDL allows data to be represented in terms of
high-level data types. A data type is an abstract representation of stored data, such as you might
encounter in software languages. These data types might represent individual wires in a circuit, or they
might represent collections of wires.
The preceding description of the comparator circuit used the data types bit and bit_vector for its inputs
and outputs. The bit data type has only two possible values: '1' or '0'. (A bit_vector is simply an array of
bits.) Every data type in VHDL has a defined set of values, and a defined set of valid operations. Type
checking is strict, so it is not possible, for example, to directly assign the value of an integer data type
to a bit_vector data type. (There are ways to get around this restriction, using what are called type
conversion functions.
The chart below summarizes the fundamental data types available in VHDL.
Data Type
Values
Example
Bit
'1', '0'
Q <= '1';
Bit_vector (array of bits)
DataOut <= “00010101”;
Boolean
True, False
EQ <= True;
Integer
-2, -1, 0, 1, 2, 3, 4 . . . Count <= Count + 2;
Real
1.0, -1.0E5
V1 = V2 / 5.3
Time
1 us, 7 ns, 100 ps
Q <= '1' after 6 ns;
Character 'a', 'b', '2, '$', etc.
CharData <= 'X';
String
(Array of characters)
Msg <= “MEM: “ & Addr
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VHDL Language Reference
Notes
The VHDL symbol <= is an assignment operator that assigns the value(s) on its right to the variable on
its left.
Design Units
One concept unique to VHDL (when compared to software programming languages and to its main
rival, Verilog) is the concept of a design unit. Design units in VHDL (which may also be referred to as
library units) are segments of VHDL code that can be compiled separately and stored in a library.
There are actually five types of design units in VHDL;
entities
,
architectures
,
packages
,
package
bodies
, and
configurations
. Entities and architectures are the only two design units that you must
have in any VHDL design description. Packages and configurations are optional.
Entities
A VHDL entity is a statement (indicated by the
entity
keyword) that defines the external specification of
a circuit or sub-circuit. The minimum VHDL design description must include at least one entity and one
corresponding architecture.
When you write an entity declaration, you must provide a unique name for that entity and a port list
defining the input and output ports of the circuit. Each port in the port list must be given a name,
direction (or mode, in VHDL jargon) and a type. Optionally, you may also include a special type of
parameter list (called a generic list) that allows you to pass additional information into an entity.
An example of an entity declaration is given below:
entity
fulladder
is
port
(X:
in
bit;
Y:
in
bit;
Cin:
in
bit;
Cout:
out
bit;
Sum:
out
bit);
end
fulladder;
Architectures
A VHDL architecture declaration is a statement (beginning with the
architecture
keyword) that
describes the underlying function and/or structure of a circuit. Each architecture in your design must be
associated (or bound) by name with one entity in the design.
VHDL allows you to create more than one alternate architecture for each entity. This feature is
particularly useful for simulation and for project team environments in which the design of the system
interfaces (expressed as entities) is performed by a different engineer than the lower-level architectural
description of each component circuit, or when you simply want to experiment with different methods of
description.
An architecture declaration consists of zero or more declarations (of items such as intermediate
signals, components that will be referenced in the architecture, local functions and procedures, and
constants) followed by a
begin
statement, a series of concurrent statements, and an
end
statement, as
illustrated by the following example:
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architecture
concurrent
of
fulladder
is
begin
Sum <= X
xor
Y
xor
Cin;
Cout <= (X
and
Y)
or
(X
and
Cin)
or
(Y
and
Cin);
end
concurrent;
Packages and package bodies
A VHDL package declaration is identified by the
package
keyword, and is used to collect commonly-
used declarations for use globally among different design units. You can think of a package as a
common storage area, one used to store such things as type declarations, constants, and global
subprograms. Items defined within a package can be made visible to any other design unit in the
complete VHDL design, and they can be compiled into libraries for later re-use.
A package can consist of two basic parts: a package declaration and an optional package body.
Package declarations can contain the following types of statements:
•
Type and subtype declarations
•
Constantdeclarations
•
Global signal declarations
•
Function and procedure declarations
•
Attributespecifications
•
Filedeclarations
•
Componentdeclarations
•
Aliasdeclarations
•
Disconnectspecifications
•
Useclauses
Items appearing within a package declaration can be made visible to other design units through the
use of a
use
statement.
If the package contains declarations of subprograms (functions or procedures) or defines one or more
deferred constants (constants whose value is not immediately given), then a package body is required
in addition to the package declaration. A package body (which is specified using the
package body
keyword combination) must have the same name as its corresponding package declaration, but it can
be located anywhere in the design, in the same or a different source file.
The relationship between a package and package body is somewhat akin to the relationship between
an entity and its corresponding architecture. (There may be only one package body written for each
package declaration, however.) While the package declaration provides the information needed to use
the items defined within it (the parameter list for a global procedure, or the name of a defined type or
subtype), the actual behavior of such things as procedures and functions must be specified within
package bodies.
An example of a package is given below:
package
conversion
is
function
to_vector (size: integer; num: integer)
return
std_logic_vector;
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